-----------------------------------------------------------
--Archivo: cell.vhd 		                 --
--Fecha de creación: 01/10/2010				 --
--Última fecha de modificación: 01/10/2010		 --
--Diseñador: Jesus Perez				 --
--Diseño: Celda SRAM.				 --
--Propósito: Celda de Memoria Estatica para la creacion  --
--	de una SRAM  					--
-----------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity cell is
  port(
    INPUT        : in  std_logic;
    CELL_ENABLE  : in  std_logic;
    WRITE_ENABLE : in  std_logic;
    CLK          : in  std_logic;
    OUTPUT       : out std_logic
  );
end cell;

architecture structural of cell is

  component ffd
    port(
      D   : in  std_logic;
      E   : in  std_logic;
      CLK : in  std_logic;
      Q   : out std_logic      
    );
  end component;

  component tri_state
    port(
      I : in std_logic;
      E : in std_logic;
      O : out std_logic
    );
  end component;

  component and_gate
    port(
      A : in std_logic;
      B : in std_logic;
      C : out std_logic
    );
  end component;

  signal and_out : std_logic;
  signal ffd_out : std_logic;

begin

  ffd1 : ffd port map(
    D   => INPUT,
    E   => and_out,
    CLK => CLK,
    Q   => ffd_out
  );
    
  tri_state1 : tri_state port map(
    I => ffd_out,
    E => CELL_ENABLE,
    O => OUTPUT
  );
  
  and_gate1 : and_gate port map(
    A => CELL_ENABLE,
    B => WRITE_ENABLE,
    C => and_out
  );

end structural;
